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Documentation
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NAME
libpfm_intel_snb - support for Intel Sandy Bridge core PMU
SYNOPSIS
#include <perfmon/pfmlib.h>
PMU name: snb
PMU desc: Intel Sandy Bridge
DESCRIPTION
The library supports the Intel Sandy Bridge core PMU. It should be noted that
this PMU model only covers the each core's PMU and not the socket level
PMU. This PMU model covers only th single socket Sandy Bridge processors, a.k.a.,
Intel Core I7 2xxx series.
On Sandy Bridge, the number of generic counters depends on the Hyperthreading (HT) mode.
When HT is on, then only 4 generic counters are available. When HT is off, then 8 generic
counters are available. The pfm_get_pmu_info() function returns the maximum number
of generic counters in num_cntrs.
MODIFIERS
The following modifiers are supported on Intel Sandy Bridge processors:
- u
-
Measure at user level which includes privilege levels 1, 2, 3. This corresponds to PFM_PLM3.
This is a boolean modifier.
- k
-
Measure at kernel level which includes privilege level 0. This corresponds to PFM_PLM0.
This is a boolean modifier.
- i
-
Invert the meaning of the event. The counter will now count cycles in which the event is not
occurring. This is a boolean modifier
- e
-
Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier.
- c
-
Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles
in which the number of occurrences of the event is greater or equal to the threshold. This is an integer
modifier with values in the range [0:255].
- t
-
Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier.
OFFCORE_RESPONSE_0 event
The event needs special treatment because it uses two MSRs: a generic counter and MSR @ 0x1a6.
The OFFCORE_RESPONSE_0 event is exposed as a normal event with several umasks which are divided in
two groups: request and response. The user must provide at least one umask from each group.
For instance, OFFCORE_RESPONSE_0:ANY_DATA:LOCAL_DRAM.
When using pfm_get_event_encoding(), two 64-bit values are returned. The first value, in
codes[0], corresponds to what needs to be programmed into any of the generic counters.
The second value, codes[1], must be programmed into the dedicated MSR 0x1a6.
When using an OS-specific encoding routine, the way the event is encoded is OS specific. Refer to
the corresponding man page for more information.
OFFCORE_RESPONSE_1 event
The event needs special treatment because it uses two MSRs: a generic counter and MSR @ 0x1a7.
The OFFCORE_RESPONSE_1 event is exposed as a normal event with several umasks which are divided in
two groups: request and response. The user must provide at least one umask from each group.
For instance, OFFCORE_RESPONSE_1:ANY_DATA:LOCAL_DRAM.
When using pfm_get_event_encoding(), two 64-bit values are returned. The first value, in
codes[0], corresponds to what needs to be programmed into any of the generic counters.
The second value, codes[1], must be programmed into the dedicated MSR 0x1a7.
When using an OS-specific encoding routine, the way the event is encoded is OS specific. Refer to
the corresponding man page for more information.
AUTHORS
Stephane Eranian <eranian@gmail.com>
Index
- NAME
-
- SYNOPSIS
-
- DESCRIPTION
-
- MODIFIERS
-
- OFFCORE_RESPONSE_0 event
-
- OFFCORE_RESPONSE_1 event
-
- AUTHORS
-
This document was created by
man2html,
using the manual pages.
Time: 11:46:10 GMT, March 02, 2011
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