libpfm_intel_nhm - support for Intel Nehalem core PMU
PMU name: nhm
PMU desc: Intel Nehalem
The library supports the Intel Nehalem core PMU. It should be noted that
this PMU model only covers the each core's PMU and not the socket level
PMU. It is provided separately. Support is provided for the Intel Core i7
and Core i5 processors.
The following modifiers are supported on Intel Nehalem processors:
Measure at user level which includes privilege levels 1, 2, 3. This corresponds to PFM_PLM3.
This is a boolean modifier.
Measure at kernel level which includes privilege level 0. This corresponds to PFM_PLM0.
This is a boolean modifier.
Invert the meaning of the event. The counter will now count cycles in which the event is not
occurring. This is a boolean modifier
Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier.
Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles
in which the number of occurrences of the event is greater or equal to the threshold. This is an integer
modifier with values in the range [0:255].
Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier.
Enable precise sampling for this event. On Intel Nehalem, this triggers the use of the Precise Event
Based Sampling (PEBS) mode. Not all events or unit masks support this mode. This is an integer
modifier with values in the range [0-3]. The value of this modifier determines how the skid of the
interrupted instruction address is handled by the kernel. The exact meaning of each of the four
values depends on the underlying kernel interface. For perf_events, this determines how
PERF_SAMPLE_IP is adjusted by the kernel. Refer to perf_events documentation for more details.
The library is able to encode the OFFCORE_RESPONSE_0 event. This is a special event because it
needs a second MSR (0x1a6) to be programmed for the event to count properly. Thus two values
are necessary. The first value can be programmed on any of the generic counters. The second value
goes into the dedicated MSR (0x1a6).
The OFFCORE_RESPONSE event is exposed as a normal event with several umasks which are divided in two
groups: request and response. The user must provide at least one umask from each group.
For instance, OFFCORE_RESPONSE_0:ANY_DATA:LOCAL_DRAM.
When using pfm_get_event_encoding(), two 64-bit values are returned. The first value
corresponds to what needs to be programmed into any of the generic counters. The second value
must be programmed into the dedicated MSR (0x1a6).
When using an OS-specific encoding routine, the way the event is encoded is OS specific. Refer to
the corresponding man page for more information.
Stephane Eranian <firstname.lastname@example.org>
- OFFCORE_RESPONSE event
This document was created by
using the manual pages.
Time: 11:46:10 GMT, March 02, 2011